1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a phase change random access memory (PCRAM).
2. Related Art
A PCRAM is a nonvolatile memory apparatus which programs a resistive memory cell through a programming current pulse. The PCRAM stores data using a phase change of the phase change material depending on a temperature condition. In other words, a resistance change is introduced via a phase change of a phase change material.
The phase change material may include a material which can transition into an amorphous state or crystalline state depending on a temperature condition. A representative example of the phase change material may include chalcogenide alloys such as Ge2Sb2Te5 (GST) using germanium (Ge), antimony (Sb), and tellurium (Te). Therefore, the phase change material is generally referred to as GST.
The PCRAM causes a reversible phase change between the crystalline state and the amorphous state of GST, using Joule heat generated after applying a current or voltage under a specific condition for GST. In general, the crystalline state is referred to as a set state, and GST in the set state exhibits electrical characteristics similar to a metal with low resistance. Furthermore, the amorphous state is referred to as a reset state, and a current flowing in GST in the reset state or a corresponding voltage change based on the current change is sensed to determine stored data. In general, the set state is defined to have a logic level of ‘0’, and the reset state is defined to have a logic level of ‘1’. Although power is cut off, due to its nonvolatile nature, GST continuously maintains its state.
FIG. 1 is a diagram illustrating a conventional PCRAM 10.
Referring to FIG. 1, the conventional PCRAM 10 includes a write driver 11, a sense amplifier unit 12, a switch unit 13, and a memory unit 14. The memory unit 14 includes a phase change element 141 and a diode 142.
Referring to FIG. 1, a write operation of the conventional PCRAM 10 will be described as follows.
During the data write operation of the conventional PCRAM 10, the write driver 11 is enabled to supply a program current I_PGM (not shown) to the switch unit 13.
During the data write operation of the conventional PCRAM 10, a first select signal GYSWP transits to a low level to form a current path through which the program current I_PGM is passed from the write driver 11 toward the memory unit 14.
In order to improve the drivability of the write driver 11 during the data write operation of the PCRAM 10, a current outputted from the sense amplifier unit 12 is used to precharge a bit line BL (not shown). A second select signal GYSWN in a logic high state may then be applied to the switch unit 13 to form a current path between the sense amplifier unit 12 and the memory unit 14.
In the conventional PCRAM 10, however, parasitic capacitance may accrue in the current path during the write operation. Therefore, it may take a long time to store data in the memory unit 14, and a fail bit may occur when data is stored.